1. Field of the Invention
The present invention relates to delaying data strobe signals to register incoming data on both edges of the strobe and to send write data and write data strobes to be captured by another device.
2. Description of the Related Art
Double data rate (DDR) memory devices read and write data on both the positive and negative edges (transitions) of a clock signal. Thus, DDR memory provides twice the data rate of memory devices that only read and write data on the positive edge of a clock signal. Along with the increased bandwidth, the DDR memory substantially increases the complexity of the memory subsystem. Since two data words are now sent every clock cycle as opposed to one in a single data rate device, the data eye, or window during which the data can reliably be captured, is significantly reduced. For example, FIG. 1A illustrates a clock signal and a data trace for a single data rate memory and a double data rate memory. As illustrated, the single data rate memory reads/writes one word per clock cycle while the double data rate device reads/writes two words per clock cycle. Thus, the data eye for data in a single data rate memory is much larger than the data eye for data from a double data rate memory. This aspect of the DDR design significantly increases the complexity of the timing considerations for reading and writing data to and from the DDR memory.
A memory controller can be used to interface between the DDR memory and an application specific integrated circuit (ASIC). The memory controller is used to interface to the DDR memory by providing the write data, write data strobe and other write commands to the DDR memory with the appropriate timing relationships such that the data can be reliably written to memory. The memory controller can also be used to capture read data received from the DDR memory during a read operation.
When data is written to a DDR memory, a write data strobe and the corresponding write data are sent to the DDR memory. The DDR memory uses the write data strobe to capture the write data so that it can be written to memory. The DDR memory assumes that the write data strobe is aligned with the data eye of the write data, therefore, the memory controller must output the write data strobe and the write data to the DDR memory with the appropriate timing relationship. This can be accomplished by delaying a clock signal in the memory controller, which has the same frequency as the DDR memory clock, so that the clock aligns with the data eye of the write data. The delayed clock signal is then output of the controller as the write data strobe along with the write data. It is assumed that the wires for the write data and the associated write data strobe are routed with the same length between the controller and the DDR memory device to ensure proper timing when the signals reach the DDR memory.
To reduce complexity, DDR memory devices typically require the write data strobe to arrive at the DDR memory within some percentage of the rising edge of the master clock for the DDR memory. Typically, DDR memory devices require the write data strobe to arrive at the DDR memory within xc2xc of the rising edge of the DDR master clock. For this reason, the amount of delay applied to the write data strobe depends on the distance the signal must travel from the memory controller to the DDR memory device. This distance is often referred to as flight time. Often times, this requirement requires the design of the DCC to be specialized for each ASIC board design since board designs typically vary in the amount of flight time between the memory controller and the DDR memory. This is inefficient and costly.
During a read operation, the memory controller recieves read data along with a read data strobe from the DDR memory. The DDR memory sends the read data strobe coincident with the read data. In other words, the rising edge of the read data strobe arrives at the memory controller at the same time that the read data is in transition. In order to reliably capture the read data, the memory controller needs to align the read data strobe with the data eye of the read data.
FIG. 1B illustrates the relationship between the read data strobe and the read data in greater detail. The rising and falling edges 110 and 120 of the read data strobe sent by the DDR memory are not aligned with the data eye of the read data. Instead, the rising and falling edges occur when the read data is in transition. In order to reliably capture the data, the read data strobe must be delayed so that the rising and falling edges of the read data strobe are aligned with the data eye of the read data.
Since the read data strobe and the read data are coincident when sent from the DDR memory, it is assumed that the wires for the data and the associated read data strobe are routed with the same length between the controller and the DDR memory device. In other words, the controller assumes that the read data strobe and the read data are coincident when they are received at the controller. If they are not coincident, the delay applied by the controller may not align the read data strobe with the data eye of the read data. This will reduce the reliability of the read data capture.
In order to align the read data strobe with the data eye of the read data, the read data strobe needs to be delayed in the memory controller. The amount of delay applied to the read data strobe depends on the type of DDR memory device being used. The data eye during which the read data can be captured varies for different DDR memory devices. Some devices specify the data eye more towards the rising edge than the falling edge and vice versa. Thus, the amount of delay that needs to be applied to the read data strobe varies for different DDR memory devices. Again, to meet these design requirements, the delay circuitry must often be redesigned for each type of DDR memory that is used in the memory subsystem.
What is needed is a delay circuit that can be programmed to provide varying amounts of delay to read and write data strobes depending on the board design and DDR memory that is being used in a particular application. Such a delay circuit would allow the memory controller to be reused across different board designs, thus saving development time and costs.
The present invention relates to circuitry for delaying a clock signal according to a delay value that can be programmed external to the circuitry. The delay locked loop (DCC) of the described embodiment determines the number of delay elements required to capture a clock cycle of a clock signal. The DCC uses the number of delay elements and a received programmable delay value to determine how many delay elements are required to delay the clock signal by the programmable delay value. The DCC delays the clock signal by passing the clock signal through the number of delay elements needed to delay the clock signal by the programmable delay value.
In one embodiment, the delay circuitry is used in a memory controller to interface with a DDR memory. The delay circuitry is used to delay a read data strobe received from the DDR memory coincident with the read data during a read operation. The read data strobe is delayed by a received programmable delay value so that the rising and falling edges of the read data strobe align with the data eye of the read data. In another embodiment, the delay circuitry is used to delay an internal clock signal in a memory controller that has the same frequency as the master clock of a DDR memory the memory controller is interfacing with. The delayed master clock is the write data strobe sent to the DDR memory with the write data during a write operation. The rising edge of the write data strobe is aligned with the data eye of the write data so that the DDR memory can reliably capture the write data.
One advantage of the present invention is that the programmable nature of the DCC allows the ASIC to be used with varying board designs and memory devices. The delay applied by the DCC is programmed to compensate for the flight time between the memory controller and the DDR memory. Another advantage of the present invention is that the delay values are updated in the DCC when the DDR DRAM memory is in a refresh cycle. During the refresh cycle, no data strobes are delayed in the DCC. As a result, the DCC does not introduce jitter or glitch into the delayed data strobes. This significantly reduces the complexity of the circuitry by eliminating the need for special analog circuitry to monitor for the introduction of jitter or glitch into the delayed data strobes.